speed multiplier

The FPGA hardcore resources were used less as far as possible during the whole system designed, and the multiplier which occupy more resources and had slower speed was not used, parallel input and pipelining technology were used to improve the running speed of circuit.

整个系统设计时都尽量少用FPGA的硬核资源，并且没有使用占用资源多，速度较慢的乘法器的使用，同时还采用了并行输入方式和流水线技术来提高电路的运行速度。

The algorithm does not use any multiplier so that the speed of computation has been accelerated.

该算法在运算过程去除了所有的乘法器在运算过程中没有使用乘法器,使得运算速度得到较大地提高.

In order to increase training speed of original on-line support vector machine training algorithm, and to deal with the case of margin support vector set being empty, a new algorithm was obtained by strict mathematical deduction based on KKT condition and Lagrangian multiplier method.

针对支持向量机在线训练算法训练速度较慢和无法处理边缘支持向量集合为空的缺点，以KKT条件和拉格朗日乘数法为基础，用严格的数学推导得到一种改进的训练算法。

Operating at clock speed of 50 MHz in FPGA, the multiplier can meet the demand of DTR.

该乘法器在工作频率为50MHz的FPGA芯片中工作正常, 可以满足光盘的DTR要求.

Second, this paper proposes two kinds of decision-making methods, non-difference curve methods and Lagrange multiplier methods. The optimal decision of speed of economic increase and surplus is made in terms of SEEM curve and Non-difference curve.

根据SEEM特性曲线和由效用函数得到的无差异曲线，提出了用于决策的无差异曲线法和拉格朗日乘数法，并据此得到了最优的经济增长速度和经济剩余组合决策；